1. Field of the Invention
The present invention relates to a method for producing an active matrix substrate for use in liquid crystal display devices.
2. Description of the Prior Art
It is known in the art that an active matrix substrate has a relatively large single substrate on which a plurality of gate buses and source buses are arranged in a matrix and a pixel electrode formed in an area enclosed by the gate and source buses, and the pixel electrode is driven by a thin film transistor (TFT) disposed adjacent to the junctions of the gate bus and the source bus. The TFT is electrically connected to a gate electrode connected to the gate bus, and a source electrode, and a drain electrode is connected to the source bus to which the pixel electrode is electrically connected.
Referring to FIGS. 32A and 32B, a typical example of fabricating the known active matrix substrate will be described:
As shown in FIG. 32A, a gate electrode 102 is formed on a glass substrate 101 on which a gate insulating layer 103 is then formed. A semiconductor layer 104 is formed on the gate insulating layer 103. A channel protective layer 105 is patterned on the semiconductor layer 104 in an area corresponding to the gate electrode 102. Finally, P.sup.+ ions are implanted to form contact layers 106a and 106b in the semiconductor layer 104.
Unnecessary parts of the contact layers 106a and 106b are removed by a photolithographic method and etching to pattern the contact layers 106a and 106b shown in FIG. 32B. FIG. 33 shows a finished state in which a source electrode 107 and a drain electrode 108 are patterned.
The substrate 101 is wholly covered with an inter-layer insulating layer 109 having a contact hole 111 through which the pixel electrode is electrically connected to the drain electrode 108. In this way an active matrix substrate is obtained.
This type of known active matrix substrate is disadvantageous in that an area around the contact layers 106a and 106b is liable to damage when P.sup.+ ions are implanted into the semiconductor layer 104 to form these layers, and that this area is liable to the spread of the carrier.
Particularly in FIG. 33, if the insulating layer 103 situated in an area in which the gate electrode 102 and source electrode 107 overlap each other, or in which the gate electrode 102 and drain electrode 108 overlap each other is damaged, the desired transistor characteristics of the TFT is not achieved because of a shift in the threshold voltage which is likely to occur because electrons are trapped in the gate insulating layer 103. This results in an unstable operation.
In order to solve this problem, one proposal is that as shown in FIG. 34, a doping is carried out at a low accelerating voltage so as to prevent impurities from reaching the gate insulating layer 103 when P.sup.+ ions are implanted. However, under this method, as shown in FIG. 34A, the semiconductor layer 104 has contact layers 106a and 106b which do not reach the gate insulating film layer 103. If this semiconductor layer 104 is patterned as shown in FIG. 34B, the contact layers 106a and 106b are not formed on the sides of the semiconductor layer 104. If, as shown in FIG. 35, the source electrode 107 and drain electrode 108 are patterned on the contact layers 106a and 106b, electric leakage is likely to occur between the contact layer 106a and the source electrode 107, and between the contact layer 106b and the drain electrode 108, thereby deteriorating the transistor characteristics.
In addition, this known method detrimentally allows the spreading of impurities into the channel protective layer 105 when P.sup.+ ions are implanted on the patterned protective layer 105. The impurities in the channel protective layer causes an electric current to leak between the contact layer 106a and the source electrode 107, and between the contact layer 106b and the drain electrode 108, thereby deteriorating the transistor characteristics.
A further problem is that as shown in FIG. 36, the semiconductor layer 104 and source electrode 107 are located excessively near to each other with only the interposition of one end of the channel protective layer 105. Likewise, the semiconductor layer 104 and drain electrode 108 are located excessively near to each other with only the interposition of the other end of the channel protective layer 105. As a result, an electric leakage is likely to occur between the source electrode 107 and drain electrode 108, thereby causing a malfunction in the display operation. The leakage tends to occur and continue in the area indicated by the arrow in FIG. 36 because of the non-presence of contact layers 106a and 106b in this area.
In recent years, a large-capacity active matrix display device for use in a high definition (ED) TV set, a graphic display device, and the like has been developed and used. The known TFTs can not be used for such large-capacity active matrix display devices in that an electric leakage of 10.sup.-9 to 10.sup.-11 A occurs.
In order to prevent the occurrence of leakage, Japanese Patent Laid-Open Publication No. 3-4566 discloses a TFT having a structure in which contact layers having a distribution of impurities of low concentration are formed by implanting ions between the semiconductor layer and the source electrode, and between the semiconductor layer and the drain electrode. This TFT structure advantageously removes non-linear currents occurring by contact between the electrodes constituting the source area or drain area of the transistor and the semiconductor layer, and an off-current generated by the flow of electrons and holes caused by the irradiating of the semiconductor layer. This shortens the channel of the TFT, but on the other hand, the number of processes and photomasks are increased, thereby reducing production yield and reliability